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Altera_Forum
Honored Contributor
Honored Contributorderived clock versus clock enable
Hello, please can anyone post good links toward this problem. So far I have read that clock enable is the best solution if I need a divided clock. There is a communication between the 2 (s...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- 2) using a clock enable and set a multicycle constrain --- Quote End --- what is this multicycle constrain ?? I also need to divide 16Mhz clock to 500Khz currently I made 4bit counter (count to 16) and then connected counter output to this global clock network and quartus shows this warning about clock skews and so on. I tried to use PLL but with PLL I can lower clock frequency just to 10Mhz :( what is the right way for clock division ??
