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Timing constraints can kept only within the capabilities of the hardware to my opinion. When routing a PLL output to pin, no logic cells are involved except for the output cell. Also the GLCK path has probably no routing alternatives in this case. So the variable small output pin delay would be the only means to adjust timing.
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I think you are right. I was thinking in the possibility of not using the global clock network, which might be even better in this case because there would be a single fanout. But I see it is forced, the PLL can only drive a clock control block, it can't drive the interconnect. Then routing would be always the same. The only variable would be exactly which clock control block is used, but this shouldn't be too significant for a specific PLL.
I guess the right thing to do would be to contraint the skew between both output pins.
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