Deos the plls of a fpga exactly same?

I reviewed PLL areset operation and can't dissipate your doubts regarding reliable synchronisation of multiple PLLs. Cause areset is apllied to all PLL counters, not only postscaler, a loss of lock is forced. The VCO is started on areset release with an arbitrary frequency. Depending on dynamic behaviour of the individual PLLs, a different number of clock pulses could be skipped before synchronisation. This suggests, that my results may be only by chance.

With Cylone III, PLL dynamic phase align can be used to synchronize divided clocks. With Cyclone II areset could be asserted repeatedly with varying delay to a single PLL until synchronisation is achieved.

Timing constraints can kept only within the capabilities of the hardware to my opinion. When routing a PLL output to pin, no logic cells are involved except for the output cell. Also the GLCK path has probably no routing alternatives in this case. So the variable small output pin delay would be the only means to adjust timing.

On the other hand, I wouldn't expect large delay variations for clock output from regular I/O. Quartus Megafunctions, e. g. DDR2 controller are intentionally using clock output from I/O pins to reduce clock to datapath skew.