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Altera_Forum
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18 years ago

Deos the plls of a fpga exactly same?

Hi, I have questions about pll. 1. If I use one clock source(27MHz) driving two plls in one fpga, and the parameter of plls is the same(generate 135MHz, but phase is same or different), Can ...
Altera_Forum's avatar
Altera_Forum
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18 years ago

FvM,

Very interesting idea, but seems dangerous to use without confirmation from Altera this is by design and reliable.

I think I will have to live without using the dedicated PLL output pins. Not that bad as long as I can constrain the routing delay. Is it possible to constrain the routing delay between the PLL output and a specific pin? The alternative would be to use back-annotated routing, but this is something I'd really like to avoid.