Deos the plls of a fpga exactly same?

I found that applying areset released synchronously to inclk was sufficient to achieve equal phase for divided outputs of two Cyclone II PLLs. Also delaying areset for a PLL by one clock cycle resulted in a reproducable phase shift.

Further investigation could be necessary to confirm that the reported behaviour is stable and not affected by minimal routing delays. In an optimistic interpretation the behaviour is by design and reproducable under usual conditions.