Deos the plls of a fpga exactly same?

There is no "start" with the PLL. So if the clock you drive them with has edges at 0ns, 10, 20, 30, 40, 50, 60... When you create a divided down PLL, say a divide by two, it might have edges at time 0ns, 20, 40, 60... or at 10ns, 30ns, 50ns...

Now technically, the clock is a continuously running thing, so there isn't any difference between these two scenarios in the system. But if two different PLLs are creating divide by two clocks, they may create clocks whose edges are aligned, or clocks who are off by 10ns. It will be different every time you power-up the PLL.

Here's the design that will synchronize them. (It's a trick, but it will work...)

http://www.alteraforum.com/forum/showthread.php?t=1473&highlight=divide+pll