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Altera_Forum's avatar
Altera_Forum
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18 years ago

Deos the plls of a fpga exactly same?

Hi, I have questions about pll. 1. If I use one clock source(27MHz) driving two plls in one fpga, and the parameter of plls is the same(generate 135MHz, but phase is same or different), Can ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

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If driving multiple PLLs with the same clock, you can't ever consider divided clocks as the same, as the PLLs may create them on different phases. (I can explain it if it doesn't make sense, and have a design to get around this issue.)

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Would you mind elaborating on this? Is it possible to phase align the output of two different PLLs driven by the same clock, when using division?