Deos the plls of a fpga exactly same?

Hello,

I think, you are unable to treat the second clock as the same clock, alt least not in timing analysis, cause the analyzer knows as well as you that it isn't. You either could treat it as unrelated (asynchronous) or as related clock with known timing. If both are derived from the same input clock in one FPGA, the timing analyzer knows the nominal timing and could consider it. If the PLL looses lock (or in case of two PLLs, one is reset), then the nominal timing would invalid, but most designs with mutiple clock domians ore multi-phase clocks are based on the assumption, that nominal phase relation is kept from startup.

In case of an external clock derived from the same reference clock, you could also assume a nominal timing relation, but with larger tolearances. For timing analyzes, you have to describe the phase relation of external clock ("constrain" it), cause the timing analyzer can't know about. This is obviously different from treating it as the same clock.

As an alternative, you could treat signals based on the external clock as unrelated, using appropriate synchronisation techniques. But you get an issue with multi-bit signals that should be processed consistently.

Regards,

Frank