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Honored Contributor

16 years ago

Demultiplexer with latched value

I am using a demultiplexer with six output registers. The code is pretty simple. process(X,sel) begin case sel is when "000"=> A <=X; when "001" => B <=X; when "01...

Altera_Forum

Honored Contributor

16 years ago

Hi,

Have a read of http://www.altera.com/literature/hb/qts/qts_qii51007.pdf page 42 it explains why latches are a bad idea. In short FPGAs are built out of storage elements that are all connected to a common clock.

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Demultiplexer with latched value

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