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Altera_Forum
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14 years ago

Delay chain design?

Hi I am using the cycloneIII 3c120 kit to learn designing with FPGA. What I would like to do is a delay chain, in which a signal is delayed by each chain element on the order of 100..500ps...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Hi, Flexi.

Curious if and how you solved your 100-500ps resolution issue. I've done something similar in the past in a Cyclone III, IIRC, and I'm toying with it again in a Stratix IV, which is what prompted the search. I'm seeing what amounts to ~46pS per tap on average through the delay line. It's not 100% monotonic, but fairly linear, with some outliers. If you need 500ps resolution, you can probably do some post processing of the taps to get what you need.

It is, of course, very sensitive to process, voltage, and temperature. If you look at the paths with Timequest, the same paths at the fast and slow corners are about 2:1. So if you're going to use something like this, you'd best have some means of real-time, dynamic calibration.

In any case, I was wondering what you came up with, and I'd be happy to compare notes with you.

Thanks,

Matt