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Altera_Forum
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14 years ago

Delay chain design?

Hi I am using the cycloneIII 3c120 kit to learn designing with FPGA. What I would like to do is a delay chain, in which a signal is delayed by each chain element on the order of 100..500ps...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Hi FvM, hi kaz

Thank you for your information. Can one make restrictions for placing designs into specific LEs? I assume, that this would help make a more predictable behavior. As stated, I would like to measure a pulse of 1 second to a precision of about 100..500ps, which can not be done with sync design on 3c120. The idea of using delays comes from a seminar on femtosecond counters, which I found on the internet. FPGA should be ok because of the lot of cells they have... But I am a beginner...