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Honored Contributor
Honored ContributorDelay chain design?
Hi I am using the cycloneIII 3c120 kit to learn designing with FPGA. What I would like to do is a delay chain, in which a signal is delayed by each chain element on the order of 100..500ps...
Altera_ForumHonored Contributor
Honored ContributorJust a thought. If you use Serdes you may be able to do what you want. you will need to pass say 0101 pattern regularly at high speed then switch to your pulse (ORed) and convert to parallel word e.g. 32 bits then you will read the word to indicate length of your pulse, possibly a pattern like this may be read...01010111111110101...
