Delay between Input pin to output pin via single LE

Dear sir,

Is there any document which mentions the minimum & maximum propagation delay of Cyclone IV E.

I was getting in the order of min 4ns & max 7ns from Timequest analyzer without implementing any logic between input & output inside FPGA. I am trying to configure both input & output in the same bank.

We want to know what is the order of propagation delays(min, max) between input to output when the input travels through output without any logic.

Please help in this direction.

Regards,

Thulasi