Forum Discussion
Altera_Forum
Honored Contributor
10 years agoLet me focus on this issue.
if clk edge...
count := count + 83;
if reset...
count := 0;
else
if (count < 208335) then
count := 0;
...
so count starts as zero and so is always < 208335 and so should be stuck between 83 and zero. Is this really the correct copy of your code? Or am I missing something? The second issue what do mean by 60Hz and 20KHz carrier? what is your clock speed?