default values for signals

Hi all,

Let's suppose in my FPGA design I have a simple synchronous binary counter which increments on every CLK rising edge.

I have a reset pin that puts the latches in a known state (for example, if 4 bits counter: "0000").

If not physically reset, what will be the initial value for the counter?

Is it "0000" or can it be undefined? How to specify default value for signals in quartus II?

Thanks for your help

Whitebird