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Altera_Forum
Honored Contributor
Honored Contributordefault values for signals
Hi all,
Let's suppose in my FPGA design I have a simple synchronous binary counter which increments on every CLK rising edge. I have a reset pin that puts the latches in a known state (for example, if 4 bits counter: "0000"). If not physically reset, what will be the initial value for the counter? Is it "0000" or can it be undefined? How to specify default value for signals in quartus II? Thanks for your help Whitebird4 Replies
Altera_ForumOK thanks pakumpul
Whitebird- Altera_Forum
Quartus II help has a nice description on power-up state- you might want to take a look at the QII help using keywords "power-up state, specifying".
- pakumpul - Altera_Forum
OK thanks alexandre. 0 is exactly what I want.
Whitebird - Altera_Forum
your counter will be 0 after fpga powered on.
