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Altera_Forum's avatar
Altera_Forum
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19 years ago

default values for signals

Hi all, Let's suppose in my FPGA design I have a simple synchronous binary counter which increments on every CLK rising edge. I have a reset pin that puts the latches in a known state (for...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

Quartus II help has a nice description on power-up state- you might want to take a look at the QII help using keywords "power-up state, specifying".

- pakumpul