Declaring 2D Port in Verilog

Can't be done. SystemVerilog supports this but not Verilog.

Jake

// help catch undeclared wires

`default_nettype none

module my (

input wire [1:5][31:0] five_32_bit_data_busses;

output reg [1:3][15:0] three_16bit_data_busses

);

endmodule

And just like Jakob said, do NOT waste time with verilog, it's old and bad. Simply use SystemVerilog and be happy, it's almost as good as VHDL :)