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Altera_Forum's avatar
Altera_Forum
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16 years ago

Declaring 2D Port in Verilog

Hi, Anyone know, how to declare a 2-D port in Verilog. regards, freak
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Can't be done. SystemVerilog supports this but not Verilog.

Jake