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Isaacs's avatar
Isaacs
Icon for New Contributor rankNew Contributor
4 years ago

DECA Board: PLL frequency signal distortion for MHz frequencies

Hello, I'm working with the DECA board, I'm using the Basic Function to generate a PLL with the ALTPLL tool. Everything works fine with lower frequency from 1kHz-1MHz, the problem stars when I'm t...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Putting my thought anyway.

What compensation mode did you use?

Check if you are driving the PLL output clock to a FPGA pin which is creating some contention on board? Try assigning to other pin.

Check the clock internally using Signal Tap Analyzer.


Regards