DE4 - PCI port hard IP

Ok, now I am really desperate. We have acquired a new Board to make sure the other one is not broken. Even so, the error still persist. Actually, now the design only allows to be recognised by the system but no longer carries out any transmission (loopback driver does not get any reply)

Could any one tell me which are the steps (modifications) required to make the Native end point design (using MegaWizard) work on a DE4?

My steps (or at least that I am aware of) were the following:

- Generate Hard IP Pci design

- Transceiver remains in default values, but I manage to check that fast recovery and channel 0 were selected (could not find the fifo parameter)

- Hard IP, x8 Lanes, Gen2, refclk 100MHz, application clk 250MHz, test_out (9) and no reconfig

- BARs configured as [0:1] 64 bits 32KB, [2:3] 64 bits 256B, [4:5] 64 bits 32KB (as in design manual 2011)

- On device ID change it to E001 (device code searched by altpciechdma driver that performs loopback test)

- Tags 32, Timeout ABCD, MSI 4, link common clock and link port 0x01 (other features disabled)

- Maximum payload 2KB, 1 virtual channel and maximum receiver performance

- The rest of variables are left at the default value.

Once it is done, the MegaWizard provides a default project (no FPGA assigned). Using the top_example_top design (verilog) I add to the project the files demanded (including the simulation file). So far, this is enough to be able to compile the design. In order to adapt it to the DE4 board I made the following changes:

- Pin assignment:

set_location_assignment PIN_V28 -to L0_led

set_location_assignment PIN_W28 -to alive_led

set_location_assignment PIN_R29 -to comp_led

set_location_assignment PIN_P29 -to gen2_led

set_location_assignment PIN_N30 -to lane_active_led[3]

set_location_assignment PIN_M30 -to lane_active_led[2]

set_location_assignment PIN_M29 -to lane_active_led[1]

set_location_assignment PIN_N29 -to lane_active_led[0]

set_location_assignment PIN_A21 -to free_100MHz

set_location_assignment PIN_V34 -to local_rstn_ext

set_location_assignment PIN_V30 -to pcie_rstn

set_location_assignment PIN_AN38 -to refclk

set_location_assignment PIN_AG5 -to req_compliance_push_button_n

set_location_assignment PIN_AU38 -to rx_in0

set_location_assignment PIN_AR38 -to rx_in1

set_location_assignment PIN_AJ38 -to rx_in2

set_location_assignment PIN_AG38 -to rx_in3

set_location_assignment PIN_AE38 -to rx_in4

set_location_assignment PIN_AC38 -to rx_in5

set_location_assignment PIN_U38 -to rx_in6

set_location_assignment PIN_R38 -to rx_in7

set_location_assignment PIN_AT36 -to tx_out0

set_location_assignment PIN_AP36 -to tx_out1

set_location_assignment PIN_AH36 -to tx_out2

set_location_assignment PIN_AF36 -to tx_out3

set_location_assignment PIN_AD36 -to tx_out4

set_location_assignment PIN_AB36 -to tx_out5

set_location_assignment PIN_T36 -to tx_out6

set_location_assignment PIN_P36 -to tx_out7

set_location_assignment PIN_AG6 -to usr_sw[7]

set_location_assignment PIN_AH6 -to usr_sw[6]

set_location_assignment PIN_AC8 -to usr_sw[5]

set_location_assignment PIN_AB9 -to usr_sw[4]

set_location_assignment PIN_AB10 -to usr_sw[3]

set_location_assignment PIN_AB11 -to usr_sw[2]

set_location_assignment PIN_AB12 -to usr_sw[1]

set_location_assignment PIN_AB13 -to usr_sw[0]

set_instance_assignment -name IO_STANDARD "1.8 V" -to free_100MHz

set_instance_assignment -name IO_STANDARD HCSL -to refclk

set_location_assignment PIN_AN39 -to "refclk(n)"

set_instance_assignment -name IO_STANDARD "2.5 V" -to req_compliance_push_button_n

set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to rx_in0

set_location_assignment PIN_AU39 -to "rx_in0(n)"

set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to rx_in1

set_location_assignment PIN_AR39 -to "rx_in1(n)"

set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to rx_in2

set_location_assignment PIN_AJ39 -to "rx_in2(n)"

set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to rx_in3

set_location_assignment PIN_AG39 -to "rx_in3(n)"

set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to rx_in4

set_location_assignment PIN_AE39 -to "rx_in4(n)"

set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to rx_in5

set_location_assignment PIN_AC39 -to "rx_in5(n)"

set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to rx_in6

set_location_assignment PIN_U39 -to "rx_in6(n)"

set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to rx_in7

set_location_assignment PIN_R39 -to "rx_in7(n)"

set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to tx_out0

set_location_assignment PIN_AT37 -to "tx_out0(n)"

set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to tx_out1

set_location_assignment PIN_AP37 -to "tx_out1(n)"

set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to tx_out2

set_location_assignment PIN_AH37 -to "tx_out2(n)"

set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to tx_out3

set_location_assignment PIN_AF37 -to "tx_out3(n)"

set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to tx_out4

set_location_assignment PIN_AD37 -to "tx_out4(n)"

set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to tx_out5

set_location_assignment PIN_AB37 -to "tx_out5(n)"

set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to tx_out6

set_location_assignment PIN_T37 -to "tx_out6(n)"

set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to tx_out7

set_location_assignment PIN_P37 -to "tx_out7(n)"

set_instance_assignment -name IO_STANDARD "2.5 V" -to usr_sw[7]

set_instance_assignment -name IO_STANDARD "2.5 V" -to usr_sw[6]

set_instance_assignment -name IO_STANDARD "2.5 V" -to usr_sw[5]

set_instance_assignment -name IO_STANDARD "2.5 V" -to usr_sw[4]

set_instance_assignment -name IO_STANDARD "2.5 V" -to usr_sw[3]

set_instance_assignment -name IO_STANDARD "2.5 V" -to usr_sw[2]

set_instance_assignment -name IO_STANDARD "2.5 V" -to usr_sw[1]

set_instance_assignment -name IO_STANDARD "2.5 V" -to usr_sw[0]

set_instance_assignment -name IO_STANDARD "2.5 V" -to L0_led

set_instance_assignment -name IO_STANDARD "2.5 V" -to alive_led

set_instance_assignment -name IO_STANDARD "2.5 V" -to comp_led

set_instance_assignment -name IO_STANDARD "2.5 V" -to gen2_led

set_instance_assignment -name IO_STANDARD "2.5 V" -to lane_active_led[3]

set_instance_assignment -name IO_STANDARD "2.5 V" -to lane_active_led[2]

set_instance_assignment -name IO_STANDARD "2.5 V" -to lane_active_led[1]

set_instance_assignment -name IO_STANDARD "2.5 V" -to lane_active_led[0]

set_instance_assignment -name IO_STANDARD "2.5 V" -to local_rstn_ext

set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_rstn

- Another small modification is to change the RC_64BitAddress located in altpcierd_example_app_chaining so it can use 64 bits address

So far, if I didn't leftout any other modification, it was enough to use the altpciechdma driver to carry out the loop test and check the system was working. This is no longer the case. Can anyone help me out? I really can't find what wrong in such a "straight-forward" design

Thanks in advance

Arco

P.D. Attached are the warning messages obtained from compilation