Sounds like you have an modified but incomplete version of the design DE2_TOP from the DE2 system CD.
You should either go back to the original example design or look at your present one more thorougly. You didn't report the observation very clearly. What does the compiler exactly complain about?
The project folder name as such doesn't matter. But all used verilog modules should be listed in the file list of your project, missing have to be added. The project is also defining a top entity, a module with this name must be present in one of the project's design files.