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Honored Contributor
Honored ContributorDE2-70 SRAM timing question
Hi First off, I'm fairly new to FPGA programming, so I apologise in advance for any obvious questions, and thank you for your patience. So I'm currently trying to design a processor that make...
Altera_ForumHonored Contributor
Honored ContributorDo you have the datasheet for the SSRAM part on this board? I believe this is the one: http://www.issi.com/ww/pdf/61vps_lps-51236a_102418a.pdf
It is a 5ns minimum clock cycle synchronous SRAM, so everything will happen coincident to the clock you provide the device, as the timing diagrams illustrate.
