DE2-70 SRAM timing question

What entity is going to look at the flag you're intending to raise? A Nios processor? Or some other internal logic?

Accessing external SSRAM won't incur any 'significant' delay. Unless you're hoping to operate your logic/Nios at a very high clock frequency (which will be tricky with Cyclone II), the SSRAM on that board will operate at the same frequency as your logic. SSRAMs offer single (or double) clock cycle accesses. So any flag you raise is only going to be high for 1 or 2 clock cycles. I accept burst accesses are slightly longer, but arguably still not significant.

However, if you're using Nios, it will handle these accesses without the need for a flag. If you're writing your own logic then you will design your SSRAM controller in such a way that the logic always knows where in the SSRAM access cycle it is, and when it's finished.

Cheers,

Alex