Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorDE2-115 SDRAM without NIOS
I'm trying use the SDR SDRAM on the DE2-115 FPGA development board in verilog. I can't use NIOS as the interrupts aren't fast enough for my application. As far as I can tell I have 2 options: ...
Altera_ForumHonored Contributor
Honored ContributorA day late and a dollar short probably but for what it is worth, we routinely use the Altera SDRAM controller within Qsys and without a NIOS on our boards (not DE2-115).
One example is a simple Qsys system with just the SDRAM controller and the "Avalon-MM Traffic Generator and BIST Engine" components, as a simple manufacturing diagnostic. I am not sure if there is something unique about the DE2-115 SDRAM which makes it difficult or not, but I did want to mention that in general it is easy to do option (1) in the original post. (i.e. it generally is not necessary to write your own SDRAM controller because the plain-text one from Altera works well, you can modify it if it's broken, and you don't need to use a NIOS). If you need to modify the Altera controller, or end up writing your own, one good resource (not for the chip on DE2-115, unfortunately) is the simulation models provided by Micron. In my case, we ended up using LPSDR and needed to modify the Altera SDRAM initialization sequence. Including the Micron model in the testbench was very helpful.
