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Honored Contributor
Honored ContributorDE2-115 PLL dynamic phase doesn't work at low output frequencies?
We use the ALTPLL MegaWizard Plug-in Manager to build the PLL module. We use this PLL module to generate two same frequency output clock. Then, We use the PLL dynamic phase shifting function to adjus...
Altera_ForumHonored Contributor
Honored Contributor1. To find out if it is the input frequency causing the problem, try it with higher and lower input frequencies but the same desired output frequencies.
2. Read the PLL section of the Cyclone IV handbook. It should have info about the width in bits of the multiplier and divider registers. The PLL will only generate the correct frequency if the calculated multiplier and divisor will fit into the registers. Also, look at the calculated phase resolution. You can only request phase differences that are a multiple of this. It may be rounding to zero.
