Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

DE2-115 PLL dynamic phase doesn't work at low output frequencies?

We use the ALTPLL MegaWizard Plug-in Manager to build the PLL module. We use this PLL module to generate two same frequency output clock. Then, We use the PLL dynamic phase shifting function to adjus...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi Galfonz,

Thank you very much for your reply. It is very much appreciated! I am a very beginner in FPGA.

1. Could you explain more about " if it is the output frequency itself, or the ratio of input/output frequencies."

2. When you say the low frequency might max out the PLL's register, is there anyway to check whether the low frequency max out the register?

Thanks a lot again. Looking forwards to your reply.