DE2-115 and Terasic High Speed AD/DA daughter card

Thank you much for reply. I have done some projects with DE0-Nano and it's ADC. That one is different and has a clear guidance by Altera (pins, how data transfer, and ...).

Let me explain a simple example, Consider a variable resistor and its output for using as an analog input signal for ADC. When we changes the resistance the voltage changes and of course converted bytes also. This is the first project which I want to do it by this AD/DA board and DE2-115!

As I see in the Data_conversition_HSMC_reference_manual I have Channel A and B as SMA inputs. Why two channel? Can I do it by one channel only?

And so far I have done this simple vhdl code and pin assignment just to see such a simple analog input in LEDs of DE2-115. But it doesn't work!

library ieee;

use ieee.std_logic_1164.all;

USE IEEE.NUMERIC_STD.ALL;

entity test is

port( ADA_D : in std_logic_vector (13 downto 0);

clk : in std_logic;

ADA_DCO: in std_logic;

ADA_OE : out std_logic;

ADA_OR : in std_logic;

ADA_SPI_CS: out std_logic;

AD_SCLK : inout std_logic;

AD_SDIO : inout std_logic;

AIC_BCLK : inout std_logic;

AIC_DIN : out std_logic;

AIC_DOUT : in std_logic;

AIC_LRCIN: inout std_logic;

AIC_LRCOUT: inout std_logic;

AIC_SPI_CS: out std_logic;

AIC_XCLK : out std_logic;

CLKIN1 : in std_logic;

CLKOUT0: out std_logic;

FPGA_CLK_A_N: inout std_logic;

FPGA_CLK_A_P: inout std_logic;

J1_152: inout std_logic;

XT_IN_N : in std_logic;

XT_IN_P : in std_logic;

bit_out1: out std_logic_vector (13 downto 0)

);

end test;

architecture behavioral of test is

begin

process (ADA_D)

begin

bit_out1 <= ADA_D;

end process;

end behavioral;

bit_out1 is assigned to LEDs to see the voltage changing.

I have done the pin assignment according to DE2-115 projects and I think it is fine.

I do not know where is the real input? which signal is that one?

Am I completely wrong or a part of?

Hope you can help me to solve the problem.

Thanks