DE1-SOC 5CSEMA5F31C6 can't be detected

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That looks strange - the IDCODE 2D120DD is the correct ID for 5CSEMA5F31C6. I am not sure why it is showing "unknown" in the programmer. Just to confirm, which quartus version are you using?

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I am using Quartus V 13. I have Windows 10/64 bit machine. I have one more question. I am not able generate .sof file needed to see verilog code outputs labs on the board. I am following Altera University Program Labs. Do I need any kind of license to generate the .sof files ? I am a student and I don't have enough money to buy the license. Thanks.

I am using Quartus lite 16.0 (or known as web edition, on previous versions) - and this version is free. I can generate the sof file without any issue. After I installed the University Program packages, it provided me with the IPs required for the DE1-SoC board, which again compiles just fine.

If you still encounter the same failure even in the latest version of Quartus, I suggest that you contact Terasic support for help. Perhaps they've seen cases such as this before, and is able to advise accordingly.

One more thing - make sure that you download and install the Cyclone V device support for Quartus (in Windows, it is a .qdz file) Come to think about it, this could be the reason why you are not seeing the device in the programmer....

You don't have to install the support for other devices if you are not using them (saves your hard drive space too)

Hi,

I have installed the Quartus 16.0 lite version and also University Program Installer. But how do I generate the .sof files?. Is DE1_SoC_Computer.sof (I found out in the University Program Installer folder)the file I need to add by right clicking the device every time I need to program my verilog code?. I am just implementing a simple OR gate as follows however I can't see the output on board. I have attached the picture which shows what physical pins assigned. My OR gate code is as follows:

module test_prog (x1, x2, f);

input x1, x2;

output f;

assign f = (x1 | x2);

endmodule

I have attached three snapshots of whats going on with my Quartus 16.0 Lite Edition. Please help me as I am trying very hard to see the output on DE1 SOC board. Thanks

First, I am glad to see that you are able to detect the 5CSEMA5F31C6 device using the programmer now. So that's one problem solved.

Secondly - I think you might've been confused with what the sof file does, and how to use it. I suggest going through Terasic's my first FPGA tutorial; in the meantime I will try to explain here (but trust me, it is easier to understand if you follow the guide hands on)

A sof file is a programming file that is generated each time you successfully perform full compilation of your design in Quartus. For example, let's say you implement a blinking LED using verilog code. Once you compile it, a sof file will be generated (it is usually located in the output_folder directory of your project location). Then, using the programmer, select the FPGA (put a tick box on it) and download the sof to the FPGA. Then, if everything goes well, you will see the blinking LEDs on your board.

You do not have to use the University program's DE1_SoC_computer.sof if you are writing your own verilog/hardware design in Quartus. The aforementioned sof file is provided for users who are interested to debug/learn about the software implementation in DE1-SoC. In that way, they do not have to design the system from scratch.

Hi Altera Teacher,

I am able to execute the and gate, I can see the output on the LED's. I wan't compiling my design again after the PIN assignment that is the reason I wasn't able to generate .sof files. But thanks a lot, you have really solved my problems. Have couple of beers on my name :P. Thanks.