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Altera_Forum
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10 years ago

DE0_NANO_SOC LVDS Problem

Hello, We are currently using the DE0_NANO_SOC from Terasic (http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&no=941) for our system, using the 5CSEMA4U23C6 FPGA. We runn...
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Altera_Forum
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10 years ago

Bank 4A is powered from 3.3V on the DE0-Nano-SOC. LVDS requires 2.5V. So, you probably have a mix of I/O standards, all connected to bank 4A, that require different supply voltages. So, Quartus can't solve your puzzle and throws out that error.

Unfortunately, you can't change the voltage applied to this bank, which is a shame given it only handles expansion headers.

However, the fact that this bank doesn't support anything but expansion headers offers a way around this - assuming you're not connecting anything to the Arduino headers.

In your Quartus project, remove all I/O constraints relating to this bank. Then add your clock input signals as LVDS.

Quartus will then assume that the bank is to be powered from 2.5V. Confirm this via the .pin file following compilation. You can drive LVDS into a bank powered at 3.3V.

Regards,

Alex