DE0-Nano Ethernet add on board

Dear all

I use another idea to detect the problem of RX path in my system.

this is main connection of PHY and MAC in my system:

.tse_mac_pcs_mac_tx_clock_connection_clk (TXCLK),

.tse_mac_pcs_mac_rx_clock_connection_clk (RXCLK),

.tse_mac_mac_mii_connection_mii_rx_d (RXD),

.tse_mac_mac_mii_connection_mii_rx_dv (RXDV),

.tse_mac_mac_mii_connection_mii_rx_err (RXERR),

.tse_mac_mac_mii_connection_mii_tx_d (TXD),

.tse_mac_mac_mii_connection_mii_tx_en (TXEN),

.tse_mac_mac_mii_connection_mii_tx_err (TXERR),

and i changed it to :

.tse_mac_pcs_mac_tx_clock_connection_clk (RXCLK), <--

.tse_mac_pcs_mac_rx_clock_connection_clk (RXCLK),

.tse_mac_mac_mii_connection_mii_rx_d (TXD), <--

.tse_mac_mac_mii_connection_mii_rx_dv (TXEN), <--

.tse_mac_mac_mii_connection_mii_rx_err (RXERR),

.tse_mac_mac_mii_connection_mii_tx_d (TXD),

.tse_mac_mac_mii_connection_mii_tx_en (TXEN),

.tse_mac_mac_mii_connection_mii_tx_err (TXERR),

it's just a loop-back idea. MAC receive what it sent! but it's based on RXCLK.

this test was successful and loop-back worked correctly. so i'm sure that MAC works fine!

now I'm sure that problem is in connection of MAC and PHY in RX path. but I don't understand it.

(it seems that MAC detect RXCLK but do not detect RXD and RXDV)

if there is problem in RX connection (PCB or Header pins) why Logic analyzer can detect RX signal? but MAC can not ??!

is there any other setting for FPGA pin that I missed?