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Altera_Forum
Honored Contributor
14 years agoYour two line codes after the "begin" (lines 52 and 53) don't define initial conditions, as I guess is doing the "initial" block in the Verilog code, but is permanently assigning the values "00000000000" and '0' to step and q.
You may want to put those initialisations in a reset part in each process, or just define the initial value when you declare the signal. This, for example: SIGNAL q : STD_LOGIC := '0';
SIGNAL step : STD_LOGIC_VECTOR(10 DOWNTO 0) := (others => '0');