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Altera_Forum
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14 years ago

De-interlacing ITU-BT656 525/60 in DE2_TV

Hi,

I've got trouble to find out how the ITU-BT656 525/60 can be interlaced so that it can be shown on VGA.

Here is what I've already known:

1. A image frame is 525 lines. Odd field of ITU-BT656 525/60 is from line 4 to line 265 and even field ITU-BT656 525/60 is from line 266 to line 525 and to 3.

2. From my thought, Odd field presents for line 1, 3, 5, ..., 525 on VGA that means line 4 of ITU-BT656 525/60 mentioned above is presented for line 1 on VGA, ..., and line 265 of ITU-BT656 525/60 is presented for line 525 on VGA. Similarly, Even field presents for line 2, 4, 6, ...524 on VGA that means line 266 of ITU-BT656 525/60 mentioned above is presented for line 2 on VGA, ..., and line 3 of ITU-BT656 525/60 is presented for line 524 on VGA.

Now, keeping that thinking in order to de-interlace a ITU-BT656 525/60 into VGA frame. The de-interlacing process should be:

1. Store the odd field (line 4-265) into RAM1.

2. Store the even field (line 266-525+line1,2,3) into RAM2.

3. Read RAM1 and RAM2 in turn.

However, the problem is that it is not the same solution coming from the DE2_TV box demonstration from Altera. The de-interlacing process of this code is as follow:

1. Store the odd field (line 13 - 253) into RAM1.

2. Store the even field (line 267 507) into RAM2.

3. Read RAM1 and RAM2 in turn.

I found that this way is very different from my though since it is likely unreasonable.

Can anybody help me to figure out what my problem is ?

Khai.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Sdram_Control_4Port u6 ( // HOST Side

    .REF_CLK(OSC_27),

    .CLK_18(AUD_CTRL_CLK),

    .RESET_N(1'b1),

    // FIFO Write Side 1

    .WR1_DATA(YCbCr),

    //.WR1_DATA(16'h0000),

    .WR1(TV_DVAL), //Only write YCbCr of the Active region of each line

    .WR1_FULL(WR1_FULL),

    .WR1_ADDR(0),

    //.WR1_MAX_ADDR(640*507), // 525-18

    .WR1_MAX_ADDR(0), // 525-18

    .WR1_LENGTH(9'h80),

    .WR1_LOAD(!DLY0),

    .WR1_CLK(TD_CLK),

    // FIFO Read Side 1

    .RD1_DATA(m1YCbCr),

    .RD1(m1VGA_Read),

    .RD1_ADDR(640*13), // Read odd field and bypess blanking

    //.RD1_ADDR(0),

    //.RD1_MAX_ADDR(640*253), // 253 - 13 = 240

    .RD1_MAX_ADDR(0),

    .RD1_LENGTH(9'h80),

    .RD1_LOAD(!DLY0),

    .RD1_CLK(OSC_27),

    // FIFO Read Side 2

    .RD2_DATA(m2YCbCr),

    .RD2(m2VGA_Read),

    .RD2_ADDR(640*267), // Read even field and bypess blanking

    //.RD2_ADDR(0),

    //.RD2_MAX_ADDR(640*507), //507 - 267 = 240

    .RD2_MAX_ADDR(0),

    .RD2_LENGTH(9'h80),

    .RD2_LOAD(!DLY0),

    .RD2_CLK(OSC_27),

    // SDRAM Side

    .SA(DRAM_ADDR),

    .BA({DRAM_BA_1,DRAM_BA_0}),

    .CS_N(DRAM_CS_N),

    .CKE(DRAM_CKE),

    .RAS_N(DRAM_RAS_N),

    .CAS_N(DRAM_CAS_N),

    .WE_N(DRAM_WE_N),

    .DQ(DRAM_DQ),

    .DQM({DRAM_UDQM,DRAM_LDQM}),

    .SDR_CLK(DRAM_CLK) );

    I 've tried to figure out what the problem is by modifying like the "Red" lines above. The image from camera sent out VGA should be failed since it is not written into DRAM, but it is still correct after modifying as above. It made me crazy... Could you please help me if someone know the reason ?