Ddr4 vref

Altera AFE told me that for the DQ,DM,DQS VREF is generated internally since it is POD12 standard. For command/address/control signals VREF is not needed because all this signals are output. The only signal that might need VREF is ALERT_N, but Quartus sets its standard to 1.2V not SSTL-12 so it does not use VREF. Also in the pin-out file that Quartus generates for DDR4 design all fileds for VREF pins are emtpy, whereas for DDR3 design it shows 0.75V.