Honored ContributorDoes the cyclone V (5CEFA4F23I7) support DDR3L in Hard Memory Controller ?
Handbook says: The SDRAM controller offers the following features: Low-voltage 1.35V DDR3L and 1.2V DDR3U support. But it refers to HPS, but i want to use HMC with dedicated pins and I'm not 100% sure.
Honored ContributorThe 'F' in the part number indicates up to two hard memory controllers. A quick look in Quartus tells me the particular part you've specified has 1 hard memory controller.
See: cyclone v device overview (http://www.altera.com/literature/hb/cyclone-v/cv_51001.pdf) - page 5 for an explanation of the part numbers. Regards, AlexHonored ContributorI know that my device contains one HMC.
I need to know, will my device work with DDR3L with HMC, via dedicated HMC pins on top edge of fpga.Honored ContributorUse Quartus and Qsys to help you. Put a design together in Qsys, containing the DDR3 controller configured for DDR3L. Constrain Quartus to place the memory I/O along the top edge and see if Quartus offers a fit.
I've given it a quick go, with your chosen device. It's failing to fit my design. However, the error isn't telling me the memory interface can't go on the top edge (I believe it can). I will endeavour to have another go when I have some more time. I recommend you try yourself. Regards, AlexHonored ContributorBig thanks for try :)
I already try to compile same design (i use megawizard example), but i don't have enough memory on my PC, and Fitter give me "out of memory" error:(Honored ContributorYes, it does work. I've successfully connected a DDR3L device, via the top edge, to the hard memory controller. Project attached.
Regards, AlexHonored ContributorI have new questions about HMC in Cyclone V and i ask it here. Will Cyclone V E supports both HMC working on max speed ? or just one hmc on 1 chip ?
Honored ContributorHi,
As suggested by a_x_h_75, you can know the total HMC per chip from Cyclone V overview - Sample Ordering Code and Available Options for Cyclone V E Devices From Table 4, you will be noted that A2 and A4 consists of 1 HMC while A, A7, and A9 consists of 2 HMC.Honored ContributorHonored ContributorIt should be possible to operate all the HMC' s in a particular package at max speed. As previously stated, you only have one HMC on the device you mentioned. However, the larger devices, with two, should be able to operate both at max speed.
Cheers, Alex
