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Alican's avatar
Alican
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4 years ago

DDR3 UniPHY Example Design simulation problem

I am trying to simulate my testbench based on DDR3 Example Design controller model. Briefly; I use the DDR3 memory as dual port, under "Controller Settings" tab Number of ports:2. One of them is wr...
Alican's avatar
Alican
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4 years ago

Hi again,

Thank you, I developed based on External Memory Interface Handbook from Altera and some simple reverse engineering via Questa Wave windows and some additional debug messages written by me. For example monitoring original flow; When do I have to read or drive the address, data, byte enable, etc ports of Avalon-MM... These helps me.

As a reply for your question, yes: It has worked on the real board since the beginning, It's only simulation problem. We used the Intel' s model a lot of times before but whole designs included only 1 port to read-or-write (as bidirectional). This was our first try to use dual port 1.=read, 2.=write only and then we struggled with the simulation problem. Finally the temporary solution has been found, but we hope that Intel solve this problem with any update or new Quartus version.

Regards,

Alican