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Alican's avatar
Alican
Icon for New Contributor rankNew Contributor
4 years ago

DDR3 UniPHY Example Design simulation problem

I am trying to simulate my testbench based on DDR3 Example Design controller model. Briefly; I use the DDR3 memory as dual port, under "Controller Settings" tab Number of ports:2. One of them is wr...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Alican,

I think that you need to check the Avalon Write protocol.

It's might be some operations that are not done yet.

Here some documents that might help you. Avalon Interface Specification , Avalon Verification IP

But it's also an option for you to use your own memory controller in your design.

If it's working well and has a good performance, then you can use it.

The failure only occurs in the simulation right and your board is working as expected?

Regards,

Adzim