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Alican
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4 years ago

DDR3 UniPHY Example Design simulation problem

I am trying to simulate my testbench based on DDR3 Example Design controller model. Briefly; I use the DDR3 memory as dual port, under "Controller Settings" tab Number of ports:2. One of them is wr...
Alican's avatar
Alican
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4 years ago

Hi Sir,

I couldn' t find anything to fix this problem with UniPHY IP simulation model and DDR3 memory model. I disconnected whole path among the ddr3_cv_hard memory controller and our controller block, then I developed my own Avalon-MM IP Simulation model and Memory model. After a challenging week, I got succeed. It still works well and faster than Intel' s models. Until Intel solve the problem, I consider to use my own model.

Regards,

Alican