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Alican
New Contributor
New ContributorDDR3 UniPHY Example Design simulation problem
I am trying to simulate my testbench based on DDR3 Example Design controller model.
Briefly; I use the DDR3 memory as dual port, under "Controller Settings" tab Number of ports:2. One of them is wr...
AlicanNew Contributor
New ContributorHi Sir,
My Quartus Version is 14.1 and my PLD is Cyclone-V that also called 5CGXFC9E6F31I7 part number. I tried to open debug messages as enabling verbosity bit on memory model and MagicWizard UI Option-1. But there are not any suspicious messages on the transcript. I can see CAS latency, reading data, writing data, writing or reading latencies according to memory model.
