DDR3 simulation for ArriaVSX

Hello akira,

you are right the testbench created by Quartus is not suitable for simulation of custom hardware. I changed two verilog files to adapt the DDR3 model to my project. (ddr3_1_example_sim.v in ...\ddr3_1_example_design\simulation\verilog\ and ddr3_1_example_sim_e0.v in ..\ddr3_1_example_design\simulation\verilog\submodules\)

Than I take a copy of the msim_setup.tcl (..\ddr3_1_example_design\simulation\verilog\mentor\) and extend it to compile my sources including the toplevel of my testbench.

Renaming the 3 files will prevent overriding when generating the DDR3 sim model.

Jens