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Honored Contributor
Honored ContributorDDR3 Layout Length Matching
Hello, I am laying out a DDR3 memory based on 4x 16bit chips and have seen in EMI Handbook Vol 2, Chap 4, Table 4-23 that "data, address and command signals must have matched length traces to w...
Altera_ForumHonored Contributor
Honored ContributorHi Ken,
Thank you very much I understand better. You say," if clock is external then it should be at least 20% longer. This is the case in teble 2.4 (clock is 90% longer), and fig 2.22 (clock is external)." For exemple if clock is in TOP and other in internal layer , this length must be +20% mini and +90%max. It's goodt? In MX53GU.pdf table 2-2, on line 2 "Address and Command" and line 7 "Control signals". The length recommended is between Clock (min) – 200 and Clock (min). But nothing is specified about address, command and control signals in the table 2-4. What are their lengths in table 2-4? Thank. Laurent
