Honored Contributor
Honored ContributorHi Laurent,
Yes, my original assumption was correct. The clock could have been 2" and the byte groups 1", but I did end up with them being the same at approx 2". Your question: "In MX53UG.pdf table2-1 and table 2-2 isn'tin accordance to table 2-4 can you help me please?" In table 2.4 it looks like they have used the guide form table 2.2 'routing by byte groups', as the byte groups are around 614mil, and the clock is 1175mil. This meets the requirement Byte Group max < Clock min. However note that in table 2.2 the requirement is that all byte groups are matched from group to group by 50mil, so the easiest thing is to make a lenght matching requirement for D0..31 of 25mil across the whole bank, which is what it looks like they have done (all D, DQM, DQS are within a few mil). For the FPGA design I was working on (4 chips 64 bit) I ended up with all byte group lenghts equal within each 32 bit bank. Although I did need to compensate for different lenghts on internal/external layers, as some byte groups were on external layers. [signal propogation is approx 15-20% faster on external layers due to lower dielectric as trace is in 'air'] If you keep all byte groups on internal layers, then this should not be needed, but note that if the clock is external then it should be at least 20% longer. This is the case in teble 2.4 (clock is 90% longer), and fig 2.22 (clock is external). For a very useful video on how it's done in Altium, see: http://www.fedevel.com/welldoneblog/2011/07/altium-designer-ddr3-routing-and-pcb-layout-video/ Hope this helps, Ken
