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Altera_Forum's avatar
Altera_Forum
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13 years ago

DDR3 CKE connection

Hi all,

I was looking for information on the way to connect DDR3 to Arria V, so I dowloaded the A5GX_Starter schematic and I don't understand how DDR3 CKE signal is connected to the FPGA:

The signal is pulled down through a 4.7k resitor and pulled up to "0.75V VTT" through a DNI resistor.

AFAIK DNI means Do Not Install so there are no pull up, the signal is only pulled down. However the 4.7k resistor is quite high ?

When I compare to my old FPGA design using DDR2, the DDR2 CKE signal was pulled up to VTT throught a 56Ohm.

Does anybody have an idea ? What I have to do on my new ARRIA V DDR3 schematic ?

Thanks in advance

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hi,

    I do not think you need any pull up or pull down, just connect directly from connector to FPGA IO,

    this is not only for CKE but also for all DDR3 signals, except DQ/DQS/DM that I define internal termination for my Stratix4, so I do not have any resistor on my board,

    -Akbar
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi all,

    If you look/find the DDR2, DDR3, DDR4 Board Design Guidelines document.. Specifically section 4-29 table 4-9 is about the only place that talks about CKE. For DDR2 CKE is terminated via 4.7K to ground but indicates that this guideline only applies to DDR2 and not DDR3. The DDR3 clock section of the same document says nothing of CKE..

    The Arria V GX, GT, SX, and ST Device Schematic Review worksheet (DS-01028-4.0/Page 95) calls for Unidirectional Class-I termination to VTT at the first split or division of the symmetrical tree for discrete devices.. The A5GX starter board has a provision for termination to VTT but opted (for a reason unclear) to go 4.7K to ground.

    The only reference I have located as to why 4.7K pull-down would be used on a DDR3 had to do with initial reset upon power up. The Micron spec only requires CKE to be be low 10ns before RESET#, unlike DDR2 which is longer. Aside from initial spin-up there was further information that indicated that a 4.7K pull-down could lead to poor SI on this high-frequency signal. While I realize were in Altera land, I came across a few Xilinx design notes also supporting connection to VTT.

    Still not 100% sure myself, but it appears VTT is the way to go..

    -DS