DDR3 CKE connection

Hi all,

If you look/find the DDR2, DDR3, DDR4 Board Design Guidelines document.. Specifically section 4-29 table 4-9 is about the only place that talks about CKE. For DDR2 CKE is terminated via 4.7K to ground but indicates that this guideline only applies to DDR2 and not DDR3. The DDR3 clock section of the same document says nothing of CKE..

The Arria V GX, GT, SX, and ST Device Schematic Review worksheet (DS-01028-4.0/Page 95) calls for Unidirectional Class-I termination to VTT at the first split or division of the symmetrical tree for discrete devices.. The A5GX starter board has a provision for termination to VTT but opted (for a reason unclear) to go 4.7K to ground.

The only reference I have located as to why 4.7K pull-down would be used on a DDR3 had to do with initial reset upon power up. The Micron spec only requires CKE to be be low 10ns before RESET#, unlike DDR2 which is longer. Aside from initial spin-up there was further information that indicated that a 4.7K pull-down could lead to poor SI on this high-frequency signal. While I realize were in Altera land, I came across a few Xilinx design notes also supporting connection to VTT.

Still not 100% sure myself, but it appears VTT is the way to go..

-DS