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Honored Contributor
Honored ContributorDDR2 Timing Problem in Nios System on Stratix III dev.board
Hey ... I am a student and relatively new to the FPGA topic. I have an Altera DSP development board wit a Stratix III FPGA. I'm trying since a while to create a Nios II System which uses the D...
Altera_ForumHonored Contributor
Honored ContributorThanks a lot for your answer.
I focused now a little bit more on the timing analyses. I checked the false paths and the reported the timing of my clock source. The problems are caused by the status output of the UNIPHY Controller with the outputs phy_cal_fail, phy_cal_sucess and init_reg_done. And finally in my design these outputs are connected to LEDs. I think the problem is that the Latch and Launch clock are not the same. The Launch clock is a PLL of the UniPhy Controller whereas the Latch Clock is my 50MHz Input Clock. Can you maybe give a hint how to change that? Or do you think thats may be not the reason for the problem.
