Honored Contributor
Honored ContributorLook offcourse as evident you are not meeting timing.
You have a setup failure for clk_in with a Worst case of 3.256 that means some path are violating timings. However one interesting point to see is the TNS is around 9.4ns. Well a rough guess leads me to think that there are some false paths which needs to be set because your worst case slack ie 3.2 ns is quite high comapred to your TNS. How many paths are failing in your design? Use timequest timing analyzer's report_timing option to report all the paths, because i really dont get the relation between WNS & TNS for clk_in. As you must be knowing that TNS is just the summation of all the negative slack of the failing paths. As a rough guess some 3 or 4 paths must be failing which is absurd, because quartus wont P&R in such a way that the whole design is meeting and some paths are failing that too with a -ve slack of -3.25ns. But its really hard for me to comment on the number of paths failing. Check for false paths in the design and also do report_timing and see how many paths are failing and what are the launch and latch edges (for asynchronous clock transfers)
