DDR2 pin assignment

So far in the SR the information that I have received is:

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We don't have the accessibility to disable the software check for the legality of these pin assignment. This Quartus II is develop by the engineering team. Unless a special patch is design for special case but this will have to go into special request.

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I am now inquiring if the interface is still useable, if the pins are assigned in a way that Quartus lets the compile go through, since altmemphy does some initialization and calibration when it starts. The idea is that the pins that were routed properly will still work, provided the DMs are stuck to low.