Forum Discussion
Altera_Forum
Honored Contributor
14 years agoDDR2 pin assignment
This is a very long shot, probably nobody will answer this, but here I go just in case. In Quartus II 11.1, for an EP4CGX50CF23C7 (F484 package, speed grade 7), I instantiated an altmemphy int...
Altera_Forum
Honored Contributor
14 years agoThe other possibility is that it was analyzed/tested with these I/O, and they might have better SSN, so the user might as well use them. An error is good in that it gets the user's attention so they can fix it before board layout, but is very bad after board layout. File an SR, say the board has been laid out, it's only a test, and is there any way around it. It's a hail mary, but worth a try. (For all I know, there may be a physical reason for this requirement, although it doesn't seem so on first glance...)