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Altera_Forum
Honored Contributor
Honored ContributorDDR2 pin assignment
This is a very long shot, probably nobody will answer this, but here I go just in case. In Quartus II 11.1, for an EP4CGX50CF23C7 (F484 package, speed grade 7), I instantiated an altmemphy int...
Altera_ForumHonored Contributor
Honored ContributorI got bitten by that same snake.
As Cyclone IV (and III) has no DLL there is absolutely no reason why the DQ, DQS and DM pins would be fixed to certain locations (of course other observations like SSN an DDR registers enter into the equation). AltmemPHY uses a phase-shifted PLL clock to capture the read data (DQS are only driving out). But it probably was deemed too much work to re-do the IP and the documentation proper.
