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Altera_Forum's avatar
Altera_Forum
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13 years ago

DDR2 length mathing

Hi All,

I am interfacing DDR2 to altera FPGA ""LFE3-35EA-6FTN256C"". Below i briefed & question.

Brief:

While PCB layout DDR2 signals are are grouped as below,for signal integrity & interface is properly optimized.

• Data(D0:7/DQS/DM)

• Address/Command/Clock

• Control

I am matching the length of data groups .i.e data lines [D0:7] ,DQS & DM (for example all are 1 inch trace)

I am matching the length of Address/Command/Clock group (for example all are 1.1 inch trace)

Question:

Do I need to match the trace length of Data & Address/Command/Clock groups?

(i.e both groups should be 1 inch)

Thanks & Regads

Pai

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    That part You're mentioning is Lattice part, not Altera.

    FPGA has nothing to do with length matching, so go to Micron website and read the technical documentation - it's really helpful.