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Altera_Forum
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14 years ago

DDR2 length mathing

Hi All, I am interfacing DDR2 to altera FPGA ""LFE3-35EA-6FTN256C"". Below i briefed & question. Brief: While PCB layout DDR2 signals are are grouped as below,for signal integrity ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

That part You're mentioning is Lattice part, not Altera.

FPGA has nothing to do with length matching, so go to Micron website and read the technical documentation - it's really helpful.